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Serial Translator

IP.com Disclosure Number: IPCOM000095219D
Original Publication Date: 1965-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 94K

Publishing Venue

IBM

Related People

Rohland, WS: AUTHOR

Abstract

Data represented according to the 12-bit unit record card coded is translated serial-by-bit, serial-by-digit, to binary-coded decimal B-CD form serial-by-bit, serial-by-digit. This translation is accomplished dynamically within a single nine position shift register 10. This operates in a closed loop as the translation takes place in a first cycle. Then, the B-CD data is shifted out during a second cycle with the register open-ended. In this particular example, the 12-bit code is preceded by a start bit S. The character to be translated is an X as represented by the bits 7 and 0. The bits forming the character are applied serially to terminal 11 which is connected to inputs of And's 12 and 13. The latter are conditioned by the set and reset outputs of start trigger 14, respectively.

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Serial Translator

Data represented according to the 12-bit unit record card coded is translated serial-by-bit, serial-by-digit, to binary-coded decimal B-CD form serial-by-bit, serial-by-digit. This translation is accomplished dynamically within a single nine position shift register 10. This operates in a closed loop as the translation takes place in a first cycle. Then, the B-CD data is shifted out during a second cycle with the register open-ended. In this particular example, the 12-bit code is preceded by a start bit S. The character to be translated is an X as represented by the bits 7 and 0. The bits forming the character are applied serially to terminal 11 which is connected to inputs of And's 12 and 13. The latter are conditioned by the set and reset outputs of start trigger 14, respectively. The first bit applied to terminal 11 is start bit S. And 13 passes this bit via Inverter 15 to set trigger 14 and the first position R1 of 10 via Or 16.

During time t9, only a RI Sync 1 bit is available. It is passed by And 17 conditioned by the readin signal RI to reset R1 via Or 18. As RI becomes reset, R2 is set. A RI Sync 1 pulse is available during t8 and it resets R2 so that R3 becomes set. A RI Sync 2 pulse is also available during t8. It fires single-shot SS1 and resets the triggers forming control ring 20. With SS1 fired, trigger 7, 0 of 20 is set.

The set output of trigger 7, 0 is connected to an input of And 26 and Or 27 of logic circuitry 25. The latter functions to control entry of data into register 10 and also controls the switching of parity trigger 40. And 26 functions to pass signals via Or's 28 and 29 to set positions R6 and R7 of 10. And 26 passes a signal when trigger 7, 0 is set and trigger 4-12 is reset and an input bit is passed by And
12. The S bit which enters position R1 prior to t9 and is transferred to R2 during t9 and to R3 during t8 remains in R3 during t7. This is because a RI Sync 1 pulse is not available during t7 to shift 10. However, a data bit is available during t7 and it is passed by And 26 to set positions R6 and R7. The data bit is also passed by And 30, which is conditioned at this time by R3, to set position R8.

The next RI sync 2 pulse, available during t7 and after the data bit is entered into 10, advances control ring 20 so that trigger 6, 11 is set. This provides different conditioning inputs to 25 so as to facilitate entry of a data bit into 10 at t6 if any is present on terminal 11. The register 10 is not shifted at this time.

Similarly, another RI Sync 2 pulse during t6 advances 20 so that trigger 5, 12 is set. This provides still another conditioning input to 25 in order that a data bit, if present, can be entered at t5 into 10 which remains unshifted. Another RI Sync 2 pulse occurs during t5. All positions of 20 become reset and trigger 4-12 becomes set. This trigger remains set until completion of a second burst of RI S...