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Adaptive Analog Memory

IP.com Disclosure Number: IPCOM000095227D
Original Publication Date: 1965-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Kleinfelder, WJ: AUTHOR

Abstract

This adaptive analog memory uses phase-locked oscillators PLO for both driving and sensing of the stored information. Adaptive or learning systems can automatically modify their structures to optimize performance based on past experience. The system is taught by showing it examples of input signals or patterns and simultaneously what the output is to be for each input. The system, in turn, organizes itself to comply as well as possible with what it is taught.

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Adaptive Analog Memory

This adaptive analog memory uses phase-locked oscillators PLO for both driving and sensing of the stored information. Adaptive or learning systems can automatically modify their structures to optimize performance based on past experience. The system is taught by showing it examples of input signals or patterns and simultaneously what the output is to be for each input. The system, in turn, organizes itself to comply as well as possible with what it is taught.

In this system, each memory element is made up of a pair of tape wound magnetic cores 2 and 4 as in drawing 1. These are driven via input line 6 from an RF power source not shown. Output windings 8 are arranged so that the fundamental component of the induced RF voltage cancels out. Such leaves a second harmonic distortion voltage proportional to the remanent flux in the cores. The remanent flux level can be altered by passing a DC through line 6 with a simultaneously applied RF driving signal.

The memory arrangement, as shown in drawing 2, comprises a plurality of the tape wound core units arranged in a matrix. The matrix is divided into a number of words. Each word is comprised of a plurality of core units. In each word only the first and last core units 10 and 14 are shown. Each word has a sense line, e.g., 16. This threads each core unit in a word and connects it to an output PLO 18. Sense line 16 is normally open-circuited by terminal switch 22, except when switch 22 is gated allowing a continuous circuit to be provided for line 16.

PLO 18 is constructed of the same components as each memory cell with an additional capacitor 19 being employed to provide a tuned circuit. This allows parametric oscillations to occur. A PLO driver 24, typically a gated oscillator, is connected to each PLO output via conductor 26. When PLO driver 24 is gated, an AC pump signal is applied to conductor 26 which causes phase stable oscillations to build up in each output PLO. The phase of these oscillations, as well as their rate of buildup, is used to sense the information stored in a word of memory. The oscillations are also used to change the remanent flux level in each of the memory positions.

A bias driver, e.g., 28, is connected in common to like bit positions of each word of storage. Each driver 28 is adapted, when gated, to provide a settable DC level in accordance with an energization signal on its respective input, e.g.,
30. When a driver 28 is gated, the DC level applied to a particular core unit, in combination with the AC signal from a respectively connected output PLO, acts to change the remanent flux in the core unit. This occurs only when the terminal switch for a particular word is gated. A plurality of readout drivers, e.g., 32, each of which is responsive to a binary input, drives each memory position to read out a binary signal weighted by the respective remanent flux of the core position.

During the adaption phase...