Browse Prior Art Database

Card Punch

IP.com Disclosure Number: IPCOM000095230D
Original Publication Date: 1965-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Lettieri, J: AUTHOR [+2]

Abstract

This card punch is provided with a core storage and with a left-zero punching feature. The core storage is a two-dimensional array divided into a main storage and an auxiliary storage. Each is operated in a ring or cyclic fashion and has fewer columns than does the card being punched. Data entry into and readout from main storage is under the control of cyclic input and output counters, respectively, and employs 1/2 write and full-read techniques. At the start of keying data, both counters are at the address of the same column of storage. Depression of the first data key actuates a store transfer which transfers the address of the input counter to the address register.

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Card Punch

This card punch is provided with a core storage and with a left-zero punching feature. The core storage is a two-dimensional array divided into a main storage and an auxiliary storage. Each is operated in a ring or cyclic fashion and has fewer columns than does the card being punched. Data entry into and readout from main storage is under the control of cyclic input and output counters, respectively, and employs 1/2 write and full-read techniques. At the start of keying data, both counters are at the address of the same column of storage. Depression of the first data key actuates a store transfer which transfers the address of the input counter to the address register. The keyboard also supplies 1/2 write drive current to the appropriate bit rows of main storage and actuates the input counter causing it to supply, first, a full-read current to erase the column and then a 1/2 write drive current to write the data into main, storage. Then, the input counter advances to the next column. As data keying continues, the input counter and keyboard write the data into successive columns of main storage. Should an error be noted prior to readout, the operator can depress an erase key.

This action causes an erase transfer to reset the input counter to the address stored in the address register. Subsequent keying corrects the error. After the data is keyed in, the operator presses a readout key causing the store transfer to transfer the input counter address to the address register. Due to this new address, a compare circuit feeds not-compare signals to the output counter. In response to each not-compare signal, the output counter reads the data in the addressed main storage column and then advances to the next column. The not- compare signals cease when the output counter reaches the address stored in the address register. The data read from main storage is fed through sense lines to a control which causes a card to escape or advance and have the data punched in it. Since the readout occurs independently of data keying, keying can take place during skipping, duplicating or card feeding and, as a result, the throughput of the machine is high.

A program, controlled by the position of the card being punched, defines the location and length of a left-zero field. Without regard to the length of the left-zero field, the operator first keys the significant digits into main storage and then...