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Double Poly Silicon Isolation for Integrated Circuits

IP.com Disclosure Number: IPCOM000095246D
Original Publication Date: 1965-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Doo, VY: AUTHOR [+2]

Abstract

This isolation method significantly reduces the time interval during which an N, N/+/ interface is subjected to reactor temperature. An N/+/ buried layer can be brought to the surface by a simple N diffusion and thus reduce collector resistance. The process steps permit greater tolerances among the various conductivity types with higher yields relative to other isolation methods for integrated circuits.

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Double Poly Silicon Isolation for Integrated Circuits

This isolation method significantly reduces the time interval during which an N, N/+/ interface is subjected to reactor temperature. An N/+/ buried layer can be brought to the surface by a simple N diffusion and thus reduce collector resistance. The process steps permit greater tolerances among the various conductivity types with higher yields relative to other isolation methods for integrated circuits.

A layer of an oxide of silicon, such as silicon dioxide 1-5 micron thick, is formed on a monocrystalline semiconductor wafer, preferably of N/+/ -type silicon. Subsequently, a layer of polycrystalline silicon 8-12 mils thick is deposited on top of the silicon dioxide layer as in drawing A.

The N/+/ -type silicon wafer is thinned down by lapping, polishing, and/or etching operations. Such are effected so as to maintain wafer planarity and parallelness without leaving a mechanically damaged surface layer as in B.

A thin layer of N-type monocrystalline semiconductor material is epitaxially grown on the N/+/ layer. Subsequently, a second silicon dioxide layer is grown on the N-type layer. By the usual photolithographic masking and etching techniques, a network of channels is formed through the semiconductor material to the first silicon dioxide layer. The second silicon dioxide layer is used as a mask, drawing C.

N/+/ -type regions are formed, by diffusion, in the walls of the channels thus extending the N/+/ layer...