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Performing Logic With Latch Circuit

IP.com Disclosure Number: IPCOM000095284D
Original Publication Date: 1965-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 21K

Publishing Venue

IBM

Related People

Osseck, PR: AUTHOR [+2]

Abstract

The latch circuit is set when there is a signal on line 10 and reset when there is no signal on this line. New data D enters the latch through And A1 while there is a signal on Set line 12 and no signal on Reset line 14. Latched data is maintained unchanged through And A3 when there is a signal on line 14 and no signal on line 12. The latch is reset when there is a signal on neither line 12, line 14, nor line 16. And A2 eliminates the static hazard of generating a 0 in the latch when a new 1 is to replace an existing 1 and either the signal on line 14 is dropped before a signal appears on line 12, or the signal on line 12 is dropped before a hold signal appears on line 14.

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Performing Logic With Latch Circuit

The latch circuit is set when there is a signal on line 10 and reset when there is no signal on this line. New data D enters the latch through And A1 while there is a signal on Set line 12 and no signal on Reset line 14. Latched data is maintained unchanged through And A3 when there is a signal on line 14 and no signal on line 12. The latch is reset when there is a signal on neither line 12, line 14, nor line 16. And A2 eliminates the static hazard of generating a 0 in the latch when a new 1 is to replace an existing 1 and either the signal on line 14 is dropped before a signal appears on line 12, or the signal on line 12 is dropped before a hold signal appears on line 14.

Various logic functions can be performed by manipulating the signals on lines 12 and 14. For example, new data can be Ored with the contents of the latch by simultaneously applying signals to lines 12 and 14. Similarly, new data can be Anded with the contents of the latch by not applying a signal to either line 12 or line 14. Under these conditions, the latch can be set only through And A2. By designating signals on lines 10 and 16 as the L and D conditions, respectively, the duals of the functions described above are obtained.

One advantage of the method is that, for an array of latches with common Set and Reset signals, such as for example a multibit register, only the Set and Reset signals need be controlled instead of providing Oring and Anding for each l...