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Ramp Converter with Automatic Calibration

IP.com Disclosure Number: IPCOM000095356D
Original Publication Date: 1965-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Ottesen, H: AUTHOR

Abstract

The lower drawing illustrates the operation of the analog-to-digital converter of the upper drawing. This analog-to-digital converter automatically calibrates itself each cycle.

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Ramp Converter with Automatic Calibration

The lower drawing illustrates the operation of the analog-to-digital converter of the upper drawing. This analog-to-digital converter automatically calibrates itself each cycle.

The circuit has counters M, N, K1 and K2, an oscillator having a frequency F, three comparators 1, 2 and 3, low-level switch 10, three reference voltages, ER, Ground and -EQ and a ramp generator. The counters have associated logic and the output of the comparators initiates and deactivates the counters through this logic. Comparator 1 first compares a ramp voltage to a positive reference voltage ER. When the magnitude of the ramp voltage equals the positive reference voltage ER, comparator 1 generates a signal. This activates all of the counters so that they then count the pulses generated by the oscillator.

After the ramp voltage passes the ER level, switch 10 changes the input to comparator 1 to the ground voltage. Comparator 1 generates a second signal when the ramp voltage equals the ground potential. At this time, the N counter is stopped and switch 10 switches the negative reference voltage -EQ to comparator 1. This then detects when the ramp voltage equals the negative reference voltage -EQ and terminates the action of counter M.

Two inputs are provided for unknown voltages. Input 1 is for positive unknown voltages and this input goes to comparator 2. Counter K1 begins counting pulses from the output of the oscillator when comparator 1 dete...