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Multiprocessing Instruction Buffer

IP.com Disclosure Number: IPCOM000095359D
Original Publication Date: 1965-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Meade, RM: AUTHOR

Abstract

In multiprocessing systems having two or more similar central processing units (CPU's) with shared storage, any CPU can perform any instruction of a program. The choice of a CPU for execution of an instruction is primarily based on availability. There are, however, strings of dependent instructions which can be initially assigned for processing to any CPU but which must then be all processed by the assigned CPU.

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Multiprocessing Instruction Buffer

In multiprocessing systems having two or more similar central processing units (CPU's) with shared storage, any CPU can perform any instruction of a program. The choice of a CPU for execution of an instruction is primarily based on availability. There are, however, strings of dependent instructions which can be initially assigned for processing to any CPU but which must then be all processed by the assigned CPU.

This buffer holds a sequence of instructions and assigns to any available CPU the first independent instruction. When another CPU becomes available, the buffer is scanned for the next independent instruction which is then assigned to that CPU.

Buffer stack 1 contains a plurality of buffer registers 2. Each stores an instruction word. Each independent instruction word contains a tag bit termed Beginning of String BOS. Such indication is always stored in a BOS buffer location 3 of the register 2 containing the remainder of the instruction word. The dependent instructions of a string are stored in registers 2 immediately following that of their independent instruction but do not have the BOS tag bit.

Associated with each register 2 is another tag bit storage position 4 for holding a Sequence Assigned SA bit. This can be set by any CPU when it starts processing the associated independent instruction.

Buffer stack 1 has associated with it a plurality of recycling counters to control readin to and readout of stack 1. There is a common I counter 5 and there is one E counter 6 for each CPU fed from stack 2. Each E counter 6 has a special wrap-around tag bit position 7. The I counter 5 contains the address of the register 2 which is to receive the next fetched instruction word. This counter is incremented as each new instruction word is fetched and stored. I counter 5 is reset to zero each time it tries to advance past the highest buffer address.

E counters 6 are individually set to the address of the register 2 which contains the next instruction to be transmitted to its associated CPU. Each E counter 6 has its wrap-around bit 7 set by the I counter 5 when counter 5 is reset to zero. Each E counter 6 resets its own wrap-around bit 7 when E counter 6 is reset to zero.

Decoding control network 8 is fed from all BOS positions 3 and SA positions 4 and from the I and E counters 5 and 6 to prevent erroneous operations caused by the I counter 5 overrunning one of the E counter...