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Browse Prior Art Database

Multiplex Communications Line Switch

IP.com Disclosure Number: IPCOM000095360D
Original Publication Date: 1965-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Oeters, HR: AUTHOR

Abstract

This switch transfers data received over one communication line to another communication line specified by an address received over the first communication line. Oscillator 10 drives clock 12 which steps scan counter 14 once at T5 in each clock cycle. Each position of counter 14 is associated with a particular communications line 16. Counter 14 is gated via And 18 and Or 20 to decoder 22. This selects the correct line 16 depending upon the position of counter 14. A line control word (LCW) for each line 16 is stored in a recirculating delay line memory 24. The series of LCW bits associated with lines 16 appear in a delay line window coincident with the counter 14 line designation for that line.

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Multiplex Communications Line Switch

This switch transfers data received over one communication line to another communication line specified by an address received over the first communication line. Oscillator 10 drives clock 12 which steps scan counter 14 once at T5 in each clock cycle. Each position of counter 14 is associated with a particular communications line 16. Counter 14 is gated via And 18 and Or 20 to decoder 22.

This selects the correct line 16 depending upon the position of counter 14. A line control word (LCW) for each line 16 is stored in a recirculating delay line memory 24. The series of LCW bits associated with lines 16 appear in a delay line window coincident with the counter 14 line designation for that line.

There are control bits stored in each LCW as follows. A timer field times up to a predetermined period of time, for example, twenty seconds. A sample counter field is stepped by a pulse source to cause sampling of telegraph elements at their midpoints. A shift register field receives character elements from the associated communication line. These are sampled and are shifted until a complete character is assembled in the shift register. An active bit field indicates that the channel associated with this line control word is in a transmit status. A status bit field stores specific bit configurations for control purposes. For example, a status can be idle, switch, or disconnect. An address field consists of a character which designates the communication line to which the message received over the communication line associated with this line control word is to be switched.

Each line 16 is attached to scanner 28. In this, for each line there is provided an output latch and an input line. The data in, busy in, busy out, and data out lines communicate with common control section 30. This provides multiplex logic for operations which are common to all of the lines attached to the multiplexor.

Assume that data is received over one line 16, referred to as the receiving line. During the first portion T1 of a clock cycle, when the line is scanned, the start bit, i. e., space of the first character appears on the data in line. The sample counter field is reset upon the first detected line transition from mark to space. The sample counter is then stepped via an oscillator, not shown. This adds one to the sample count each time it changes its state.

At some subsequent revolution of the delay line, the sample counter reaches a predetermined value and the start bit is sampled at its midpoint. At the time of sampling the start bit, if the busy latch for the selected line is off, it is turned on via the busy out line and the active bit for the receiving line LCW is turned on.

Subsequent bits are sampled and shifted into the shift register field of the line control word. Upon receiving a com...