Browse Prior Art Database

Fast Memory to Memory Transfer

IP.com Disclosure Number: IPCOM000095362D
Original Publication Date: 1965-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Forman, JT: AUTHOR [+2]

Abstract

Additional internal working storage S2 can be added to a central processor system designed to operate relative to a single storage array S1. The internal controls of the processor are modified to direct storage address signals SA and storage cycle request signals CR selectively to S1 or S2 instead of only to S1. Then in response to a set of signals CR and SA, the selected array cycles through a read/write sequence of activity relative to the particular address specified by SA.

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Fast Memory to Memory Transfer

Additional internal working storage S2 can be added to a central processor system designed to operate relative to a single storage array S1. The internal controls of the processor are modified to direct storage address signals SA and storage cycle request signals CR selectively to S1 or S2 instead of only to S1. Then in response to a set of signals CR and SA, the selected array cycles through a read/write sequence of activity relative to the particular address specified by SA.

By further modification of the processor controls to provide overlapped independent cycling of the two storage arrays the efficiency of operation of the processor is improved. In the example a group of words at a group of addresses SA1 in S1 is being transferred in a stream. Such transfer is to a group of addresses SA2 in S2 through gates G12. These are located between output lines of input/output buffer register BR1 of S1 and respective input lines of buffer register BR2 of S2. Cycle requests CR1 and CR2 are supplied alternately to the two arrays in timed relation to control signals supplied to the gates G12. Thus as intelligence is being regeneratively stored at address SA1, gates G12 are operated to transfer the same intelligence into BR2. S2 is operated to transfer the contents of BR2 to a corresponding address SA2 in S2.

For this operation array S1 is conditioned to operate in fetch mode. S2 is conditioned to operate in the store mode. In fetch mode the s...