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Integrated Semiconductor Structure Arrangement

IP.com Disclosure Number: IPCOM000095391D
Original Publication Date: 1965-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Phillips, RP: AUTHOR [+3]

Abstract

This integrated semiconductor structure arrangement is especially useful in fabricating an integrated circuit. Such contains a plurality of semiconductor devices each being electrically isolated from the other.

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Integrated Semiconductor Structure Arrangement

This integrated semiconductor structure arrangement is especially useful in fabricating an integrated circuit. Such contains a plurality of semiconductor devices each being electrically isolated from the other.

A substrate of semiconductor material, preferably of silicon, is provided with a network of large channels formed in one surface by using a grown silicon dioxide layer as a mask and the usual photo lithographic masking and etching techniques. Subsequently, a thin layer of monocrystalline silicon carbide material is epitaxially grown on the substrate. A thick layer of monocrystalline silicon is then epitaxially grown on the monocrystalline silicon carbide layer to a thickness greater than the depth of the originally formed channels. The excess silicon shown by the corrugated phantom line above the substrate, which is located above the land portions, is removed. Such removal by mechanically lapping and polishing techniques. The surface is cleaned with a light chemical etch. The land portion of the silicon carbide layer acts as a mechanical stop to the lapping operation due to the inherent hardness of the silicon carbide material.

Each region of silicon is now electrically isolated from the other regions of silicon since the layer of silicon carbide is an electrical insulator. Collector, emitter and base regions can be formed by the usual diffusion techniques in each isolated silicon region. The desired integrate...