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Superconductor Decoder

IP.com Disclosure Number: IPCOM000095414D
Original Publication Date: 1964-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Abrahamsen, R: AUTHOR [+2]

Abstract

Providing each cryotron of a superconductor decoder with a continuous inhibit bias allows fail-safe operation of the decoder. It also allows positive logic selection of decoder output by individual control conductors.

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Superconductor Decoder

Providing each cryotron of a superconductor decoder with a continuous inhibit bias allows fail-safe operation of the decoder. It also allows positive logic selection of decoder output by individual control conductors.

Cryotrons 1...6 used in the decoder are types which are rendered resistive by an inhibit current on a bias conductor 7. They are made superconductive by a control current on a selected control conductor, applied in bucking relationship to the inhibit current. Selection of an individual path from current source 20 of the decoder to the selected output 21...24 is thus accomplished by control signals to one cryotron in each level of logic. For example, selection of output 23 is by control currents on control conductor 12 which renders cryotron 2 superconductive, and on control conductor 15 which renders cryotron 5 superconductive. Current returns are not shown.

After each selection, when control currents are removed, the inhibit current on bias conductor 7 returns all current paths of the decoder to the resistive state. A decoder tree of ordinary cryotron gates, if used for addressing a memory plane, is subject to superconductive back-circuits if gate current fails. It could thus allow parallel superconductive paths to be set up, which would generate local persistent currents, disturbing data in the memory. With the superconductive inhibit on all gates of the decoder, a failure of current supply would result in failure to access...