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Carry Select Adder In Pulse Only Circuits

IP.com Disclosure Number: IPCOM000095424D
Original Publication Date: 1964-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Hartman, FB: AUTHOR [+2]

Abstract

This carry select adder employs pulse-only circuits and has a novel recomplementing and/or readout mechanism, carry generation and storage. Carry select adders are described in the paper in the 1. R.E. Transactions on Electronic Computers entitled Carry-Select Adder by O.J. Bedrij, Vol. EC-11, No. 3, June 1962, Pg. 340. Pulse-only circuits are described in the paper 10 Megacycle Transistorized Pulse Circuits for Computer Application by W. N. Carroll and R. A. Coopper. This was presented at the 1958 Transistor-Solid State Circuits Conference, University of Pennsylvania, February 20, 1958.

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Carry Select Adder In Pulse Only Circuits

This carry select adder employs pulse-only circuits and has a novel recomplementing and/or readout mechanism, carry generation and storage. Carry select adders are described in the paper in the 1. R.E. Transactions on Electronic Computers entitled Carry-Select Adder by O.J. Bedrij, Vol. EC-11, No. 3, June 1962, Pg. 340. Pulse-only circuits are described in the paper 10 Megacycle Transistorized Pulse Circuits for Computer Application by W. N. Carroll and R. A. Coopper. This was presented at the 1958 Transistor-Solid State Circuits Conference, University of Pennsylvania, February 20, 1958.

The carry select adder comprises an N number of 10-bit position groups. Each group has a carry 1 section 11 and a carry 0 section 12. Also, each group has a storage 1 section 13 and a storage 0 section 14. Timing signal T4 is supplied to both the carry 1 and storage I sections of each group. Each carry bit position in the groups 10... NO receives operands A, B, Read True, Read-Comp and a clear signal Clear. Inputs to the storage sections 13 and 14 include a Select 1, Select 0, respectively. Each storage bit position in the groups 10... NO receives a signal Clear. Additionally, a selected true line 15, a selected complement line 16, a carry 0 line 17 and a carry 1 line 18 shown in 25, an enlarged partial view of a 10-bit position, are supplied from the respective bit positions of the carry sections as inputs to the storage sections. The storage sections provide the sum outputs from the adder, and selected carry signals, typified by line 19, to the carry sections.

The last outputs from the carry sections of each 10-bit group are supplied as inputs to a matrix 20, together with timing signals T5 and Clear. Matrix 20 provides output signals which cooperate with a plurality of flip-flops 30...3 N. These provide the Select 1 and Select 0 signals to sections 13 and 14. Flip-flops
30...3 N also require signals Clear and T6 to provide the Select 1 and 0 signals to the respective 10-bit position groups. Each flip-flop is assigned to a particular group and provides either the Select 1 or 0 signal according to carry select operation. Matrix 20 also provides a Select 1 signal from the last 10bit position group as an input to a complementing storage unit 40. Signals T7 and Clear and an optional subtraction signal, which may or may not occur at T2, are supplied as other inputs...