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Automatic Index Reloading

IP.com Disclosure Number: IPCOM000095426D
Original Publication Date: 1964-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Amdahl, A: AUTHOR [+4]

Abstract

This high-speed, index word buffer storage supplements a larger but comparatively slow index word storage unit. The buffer storage holds the last-used index words in registers which may be read out nondestructively and rapidly. Thus, if a called-for index word is one of those stored in the buffer registers, no cycle time is required to perform a fetch from memory.

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Automatic Index Reloading

This high-speed, index word buffer storage supplements a larger but comparatively slow index word storage unit. The buffer storage holds the last- used index words in registers which may be read out nondestructively and rapidly. Thus, if a called-for index word is one of those stored in the buffer registers, no cycle time is required to perform a fetch from memory.

Main storage contains an index word portion of 256 addresses which is divided into eight areas, all addresses in an area having the three low-order bits in common. An index word register 1 is associated with each area to store the last index word fetched from the associated area. An input gate 2 for each register 1 is opened by the three low-order bits of the address of the index word called for by an instruction and places the index word on bus 3 into the assigned register 1. Simultaneously with entry of a word into a register 1, the five highorder bits of address of the word are available on a bus 4. A six-bit register 5 is associated with each register 1 and has five of its bit positions connected through a gate 6 to bus 4. Gate 6 for a register 5 is opened at the same time as gate 2 for the associated register 1. Thus, as an index word is stored in a register 1, the five higher bits of the address of the word are stored in associated register 5. Thus, the address of each stored index word is known since the five bits in a register 5 may be combined with the three low-order bits which identify the storage area to complete the address.

A sixth bit of each register 5 is for storage of a change bit which is originally set at 0 when an index word is stored in its associated register 1. It is changed to a 1 when any change is made in the index word.

An n-bit output bus 7 connects to each register 1. Such is through a gate 8 to receive a selected index word. Bus 7 passes through gate 9 to the main storage bus and through a gate 10 to the index adder for use in the next instruction. Similarly, a six-bit output bus 12 connects through gates 13 to the address registers 5. Gates 8 and 13 are opened by the same combination of three low- order bits, of the required index word address, as open gates 2 and 6 to store in registers 1 and 5. The change bit on bus 12 is connected to gate 9 as one of the control factors in operation of such gate. The five address bits on bus 12 connect to compare unit 14. This also receives the five high-order bits of the address of the required index word and indicates whether the inputs are equal or unequal. An equal indicati...