Browse Prior Art Database

Buffer Controlled Image Compression System

IP.com Disclosure Number: IPCOM000095427D
Original Publication Date: 1964-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Dodd, PD: AUTHOR [+2]

Abstract

This is a buffer system for use between a pair of asymmetrically operating devices each having a variable data flow rate. The system has digital signal source 10, including flying spot scanner 12 and coder 14, and a memory.

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Buffer Controlled Image Compression System

This is a buffer system for use between a pair of asymmetrically operating devices each having a variable data flow rate. The system has digital signal source 10, including flying spot scanner 12 and coder 14, and a memory.

Shift register buffer 16 is a queuing buffer. It receives sequential information bits from source 10 and shifts them out to the memory. Counter 18 keeps track of the present content of buffer 16 by incrementing for each input bit and decrementing for each output bit.

Gate 20 passes clock pulses cl in accordance with a predetermined count in counter 18, preferably the median count n/2. Thus, if the content of buffer 16 drops below the count n/2, cl pulses are received by scanner deflection coil drive 22. If the count is above n/2, cl pulses are not received by drive 22. Drive 22 generates a current for energizing the deflection coils of scanner 12 in ratio to the number of cl pulses received.

Thus, by adjusting the sweep rate of scanner 12, the bit rate to buffer 16 is established such as to keep buffer 16 at half capacity. As a result, the source information rate is controlled by the buffer system to coordinate with that of the memory.

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