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Clock Pulse Generation And Distribution Circuit

IP.com Disclosure Number: IPCOM000095436D
Original Publication Date: 1964-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Wolterman, AJ: AUTHOR

Abstract

This clock pulse generation and distribution circuit is for driving tunnel diode, twin-circuit logic circuitry. Such is with optimum clock pulse voltage stability and closely controlled timing of the individual clock pulse waveforms.

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Clock Pulse Generation And Distribution Circuit

This clock pulse generation and distribution circuit is for driving tunnel diode, twin-circuit logic circuitry. Such is with optimum clock pulse voltage stability and closely controlled timing of the individual clock pulse waveforms.

This is achieved by utilizing transformer 12 and a pair of symmetrical tunnel diodes 30 and 32. These are connected in series with the transformer secondary winding 20. A stable low voltage is obtained. The two symmetrical tunnel diodes 30 and 32 isolate the logic circuitry of tunnel diode twin-circuit logic elements 52 and 56 from back electromotive force developed across secondary 20 after the generation of each clock pulse voltage waveform. Resistances 50 and 54 are connected in parallel with each element 52 and 56, respectively, to preclude voltage overshoot due to distribution line inductance.

Ramp current waveform 89 is applied to transformer primary winding 14 via input terminals 16 and 18. Voltage is developed across secondary 20 at generation terminals 22 and 24. Clock pulse voltage is applied to elements 52 and 56 at distribution terminal 40.

The mirror image is applied to the logic elements at distribution terminal 36.

In operation, one tunnel diode of each element 52 and 56 changes state when secondary current 95 becomes horizontal. Then, the decrease of primary current on falling portion 93 causes a symmetrical tunnel diode 30 or 32 to change state and become a high impedan...