Browse Prior Art Database

Word Substitution Memory System

IP.com Disclosure Number: IPCOM000095486D
Original Publication Date: 1964-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Sakalay, FE: AUTHOR

Abstract

Addition of an auxiliary bit plane and unique sense line connections to a memory system allows main memory to tolerate inoperative word locations by direct reference to operative word locations in an alternate memory.

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Word Substitution Memory System

Addition of an auxiliary bit plane and unique sense line connections to a memory system allows main memory to tolerate inoperative word locations by direct reference to operative word locations in an alternate memory.

Word locations affected by inoperative bits are detected by test and marked by the setting of the related auxiliary bit storage element. The auxiliary plane may be of the read-only memory type. Each affected word has its auxiliary bit storage element directly connected to a tested good location in an alternate memory via a unique sense line.

The memory system includes main memory 1, which is subject to the presence of inoperative bit storage elements x in certain words, and alternate memory 2. Memory 1 provides output via main output register 3 and Or 4 to common bus 5. Memory 2 provides output via alternate output register 6 and Or 4 to bus 5. Memories 1 and 2 share common data entry mechanism, not shown.

Whenever a memory reference is made, addressing mechanism selects a word in main memory and reads it out. If its auxiliary bit storage element is unset, readout is normal via register 3. If its auxiliary bit storage element is set, the unique sense line selects a permanently related word in memory 2 and reads it out via register 6 and Or 4 to bus 5. The signal output of register 6 supersedes that of output register 3, by the nature of the mechanism or by the addition of gating logic as required.

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