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Automatic Correction of Burst Errors in Variable Length Serial by Bit Messages

IP.com Disclosure Number: IPCOM000095503D
Original Publication Date: 1964-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Daher, PR: AUTHOR

Abstract

This is an error checking system capable of detecting that a burst of bits of a data group is affected by error. The system is also capable of correcting it. This is accomplished in an environment in which the data group length is variable. The data group is a series of bits which represent information, the word, followed by a series of bits devoted This is an error checking system capable of detecting that a burst of bits of a data group is affected by error. The system is also capable of correcting it. This is accomplished in an environment in which the data group length is variable. The data group is a series of bits which represent information, the word, followed by a series of bits devoted to error checking.

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Automatic Correction of Burst Errors in Variable Length Serial by Bit Messages

This is an error checking system capable of detecting that a burst of bits of a data group is affected by error. The system is also capable of correcting it. This is accomplished in an environment in which the data group length is variable. The data group is a series of bits which represent information, the word, followed by a series of bits devoted This is an error checking system capable of detecting that a burst of bits of a data group is affected by error. The system is also capable of correcting it. This is accomplished in an environment in which the data group length is variable. The data group is a series of bits which represent information, the word, followed by a series of bits devoted to error checking. The check bits are derived by modulo-2 additions of information bits selected in accordance with a cyclic code. The data group length can be equal to or less than the maximum number of different bit combinations allowed by the cyclic code. In reception, a correction signal is generated as soon as the last significant bit of the data group is sensed.

Input flip-flop I1 of encoder 112 is set up to correspond to the information bits of a word and then is reset. Coincident with the receipt of the first information bit, word flip-flop W1 is set true by start-of-word signal S(W) and, after the receipt of the last bit, is reset by end-of-word signal E(W). W 1 thus indicates the serial storage of information bits in 11. Encoder register 132 has as many stages as required to provide error correction coding for a predetermined maximum number of information bits. On the desired breadth of the burst error, register 132 is arranged to sequence in response to 11 after a bit period delay provided by delay flip-flop H1. The internal feedback connections of ER 132 are made through one or more exclusive Or ( ~) gates arranged to provide operation in accordance with the selected cod...