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Delay Line Variable Clock Synchronization

IP.com Disclosure Number: IPCOM000095533D
Original Publication Date: 1964-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Bradley, EF: AUTHOR [+2]

Abstract

To maintain synchronization between data bits circulating in a solid state delay line and a master clock, having some known maximum unavoidable deviations from a nominal frequency, derived from a source such as a rotating drum or disk, an additional variable delay is provided. The data bits enter data delay line 2 through entry circuitry 1. The bits are propagated to the terminal end of the delay 2 where they are distributed bit-by-bit to the triggers in a trigger buffer 4 forming the variable delay. Such distribution is under the control of a distribution clock counter 3 which is advanced by the delayed master clock. Four triggers are shown in buffer 4 and the first bit is entered in the trigger T1, the second in trigger T2.... the fifth bit into trigger T1, etc.

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Delay Line Variable Clock Synchronization

To maintain synchronization between data bits circulating in a solid state delay line and a master clock, having some known maximum unavoidable deviations from a nominal frequency, derived from a source such as a rotating drum or disk, an additional variable delay is provided. The data bits enter data delay line 2 through entry circuitry 1. The bits are propagated to the terminal end of the delay 2 where they are distributed bit-by-bit to the triggers in a trigger buffer 4 forming the variable delay. Such distribution is under the control of a distribution clock counter 3 which is advanced by the delayed master clock. Four triggers are shown in buffer 4 and the first bit is entered in the trigger T1, the second in trigger T2.... the fifth bit into trigger T1, etc. Under the control of the master clock counter 5, which is driven by the undelayed master clock pulses, the bits are selected from the buffer triggers 4 in the same sequence as they entered, and selected bits can be either revolved or sent to the other parts of the system as determined by the condition of switch 6.

When the master clock frequency is nominal and constant, the master clock and the delayed master clock are in time coincidence. Under these conditions, data bits are selected two triggers from the one to which the incoming bit is being distributed. That is, a bit is selected from trigger T2 as a bit is distributed to trigger T4.

The delay of delay line...