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Current Driver Circuit with Controlled Charge Compensation

IP.com Disclosure Number: IPCOM000095543D
Original Publication Date: 1964-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Leilich, HO: AUTHOR

Abstract

The wire and circuit capacitance existing in large core memory assemblies is charged and discharged in controlled manner using this driver circuit.

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Current Driver Circuit with Controlled Charge Compensation

The wire and circuit capacitance existing in large core memory assemblies is charged and discharged in controlled manner using this driver circuit.

If the capacitance in the assemblies is relatively high, an additional current is required to charge and discharge the capacitance. Since this current is necessarily large, it can cause a essential deterioration of the load current waveform. If this occurs, three effects take place. There is a delay of current rise due to charging of the capacitor. Secondly, there is an overshoot of current due to the discharge of the capacitor, when the full value of current is reached. Finally, ringing occurs in the LC circuit formed by this capacitance with the inductive load elements.

The driver circuit has a transistor T2 connected in current switching arrangement with diode D1. Transistor T1 inverts the input signal to turn on T2 drawing current away from D1. When operation begins, the output voltage provided at the collector of T2 is close to ground potential and the current flow through T2 begins to rise. When T2 is fully conducting, its collector voltage tends to rise. The array bypass capacitance is charged exciting the LC circuit formed by the array inductance and this bypass capacitance.

The arrangement, including the transistors T3, T4 and T5 is employed as the charge compensating circuitry. T3 and T4 act as amplifiers to respond to the voltage jump at the emitter...