Browse Prior Art Database

Correction of Bad Bits in a Memory Matrix

IP.com Disclosure Number: IPCOM000095549D
Original Publication Date: 1964-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Sakalay, FE: AUTHOR

Abstract

Bad bit locations in a main memory are substituted with alternate bit locations in an alternate memory. Such is by direct reference from the main memory to the alternate memory whenever a bad bit location is addressed.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 88% of the total text.

Page 1 of 2

Correction of Bad Bits in a Memory Matrix

Bad bit locations in a main memory are substituted with alternate bit locations in an alternate memory. Such is by direct reference from the main memory to the alternate memory whenever a bad bit location is addressed.

Word locations in main memory affected by an inoperative bit are detected by test during manufacture of the memory. Each affected word has an auxiliary bit storage element directly connected to a good location in an alternate memory via the X-Y lines which drive the bad bit location in the main memory. The auxiliary memory can be of the read-only type.

The memory system includes main memory 10 which is subject to the presence of inoperative bit storage elements in certain words. Memory 10 provides an output via main memory output register 12 and Or 14 to a common output bus 16. Alternate memory 18 provides an output via alternate output register 20 and Or 14 to the common bus 16. Memories 10 and 18 share a common data entry mechanism, not shown. Words are selected in memory 10 by energizing X and Y selection lines, two of which are shown. The X and Y lines associated with a bad bit location are pre-wired to also energize And 22. This drives a drive circuit 24 to select an alternate word location in memory 18.

Whenever a memory reference is made, the addressing mechanism selects a word in memory 10 and reads it out. If the location contains all operative bits, readout is normal via register 12. If, however,...