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Parity Checked Digital Calculator

IP.com Disclosure Number: IPCOM000095564D
Original Publication Date: 1964-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Pugmire, JM: AUTHOR

Abstract

The apparatus performs a digit by digit addition of two operands, stores the result in one of the registers holding one of the operands, and also generates a parity check.

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Parity Checked Digital Calculator

The apparatus performs a digit by digit addition of two operands, stores the result in one of the registers holding one of the operands, and also generates a parity check.

The operands are stored respectively in a pair of arithmetic registers A and B together with corresponding parity digits. The operands are comprised of four digits, each digit comprised of four bits. Each register A and B is thus adapted to accommodate sixteen binary digits representative of the operand together with one binary digit representing the parity of the associated sixteen digits.

Table look-up storage device 10 is addressable under control of ten X address lines and ten Y address lines from address decoder 13. The output of storage accommodates the results of additions between any one of the addend numbers represented by a Y address line and any one of the augend numbers represented by an X address line. The results include on the data bus 14 a group of four bits representing a sum digit, a bit representing any carry which might be generated, and a bit indicating that a parity change has occurred.

Both shift registers A and B are arranged so that a whole decimal quantity, four bits, can be shifted right one place in response to a signal from control unit
16. In the case of register B, digits shifted from the right-hand end of the register are returned to the extreme left-hand end via feedback line 18 after each addition operation, providing in effect a circulating store.

Initially the two four-decimal digit operands stand in registers A and B with their least significant digits at the extreme right. In response to a signal from unit 16, the least significant digits of both registers are read out into the appropriate positions of address register 12. They are decoded by decoder 13 to corresponding one out of ten representations for application to the X and Y address lines of storage 10. A readout pulse is applied to storage 10 causing a word corresponding to...