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Automatic Correction of Burst Errors in Variable Length Serial by Bit Messages

IP.com Disclosure Number: IPCOM000095565D
Original Publication Date: 1964-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 5 page(s) / 163K

Publishing Venue

IBM

Related People

Daher, PR: AUTHOR

Abstract

This is an error checking system capable of detecting that a burst of bits of a data group is affected by error and of correcting it. This is accomplished in an environment in which the data group length is variable. The data group comprises a series of bits which represent information, the word, received from the data source, followed by a series of bits devoted to error checking.

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Automatic Correction of Burst Errors in Variable Length Serial by Bit Messages

This is an error checking system capable of detecting that a burst of bits of a data group is affected by error and of correcting it. This is accomplished in an environment in which the data group length is variable. The data group comprises a series of bits which represent information, the word, received from the data source, followed by a series of bits devoted to error checking.

The check bits are derived by modulo-2 additions of information bits selected in accordance with a cyclic code. The data group length can be equal to or less than the maximum number of different bit combinations allowed by the cyclic code. In reception, a correction signal is generated as soon as the last significant bit of the data group is sensed. The logic of the system reduces delay between data groups either by allowing the next data group to be sent as soon as the correction is made or it is recognized that no correction needs to be made. The arrangement of equipment is directed to a system having the following specifications: Code: x/4/ + x + 1 = 0 Cycle length: 15 Correction capability: 1 bit per data group of 15 bits Reciprocal code: x/4/+ x/3/+ 1 = 0

The data source begins transmitting a word at the digit period following the reception of ready signal R(1) from the decoder. Accompanying the first data bit is start-of-word signal S(w). Following the last, there occurs end-of-word signal E(w). The encoder accepts the word and attaches, in this case, check bits generated through operation of shift register E1... E4 to form the data group. S(w) is delayed by flip flops S1 and S2. Signal S2 is released with the first bit of the data group. The two-period delay is needed since the data bits are...