Browse Prior Art Database

Bit Synchronous Detection

IP.com Disclosure Number: IPCOM000095571D
Original Publication Date: 1964-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

McDonald, EG: AUTHOR

Abstract

In the circuit, an input line 10 receives a signal which may be derived from magnetic tape, that may be recorded, for example, as a phase encoded, or NRZI-type of signal in which any non-flux-transition bit is bounded on both sides by flux transition bits. An amplifier 11 amplifies the signal and provides opposite-phased outputs on leads 5 and 5 to the input of detector 12.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 60% of the total text.

Page 1 of 2

Bit Synchronous Detection

In the circuit, an input line 10 receives a signal which may be derived from magnetic tape, that may be recorded, for example, as a phase encoded, or NRZI-type of signal in which any non-flux-transition bit is bounded on both sides by flux transition bits. An amplifier 11 amplifies the signal and provides opposite- phased outputs on leads 5 and 5 to the input of detector 12.

Also, the signal on lead 10 is applied to variable frequency clock and synch control circuit 13. In essence, circuit 13 is an oscillator synchronized with the received signal bits. The circuit 13 output provides pulses during all bit periods for the signal on lead 10. Phase splitter 16 receives the output of circuit 13 and produces complementary synchronization outputs on leads 11 and 1 1 to the input of detector 12.

A phase ambiguity of 180 degrees can exist in the output signal from circuit 13 in relation to the signal on lead 10. This ambiguity can be resolved by selecting the proper one of two opposite-phased detector outputs on leads X and
Y. To resolve this ambiguity, a sequence of bits, such as 1 bits, are generally provided as a synchronization burst at the beginning of any block of data received by lead 10.

The choice between either the signal on output lead X or lead Y as the detected form of the data is made by binary trigger 14. If in reset status, the trigger 14 output B conditions And's 21 and 23. This results in passing X data through Or 25 to the 1's...