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System Organization for Execution of Parallel Operations in Algebraic Statements

IP.com Disclosure Number: IPCOM000095684D
Original Publication Date: 1964-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Hellerman, H: AUTHOR

Abstract

The system is a generalized machine organization for the execution of parallel operations in algebraic statements. There are included an indefinite number of processor s PROC 1... PROC N and a similar indefinite number of core memory units M1... MK as well as a Bus system tying these units to each other for data transfers. Program control is centralized in control unit 10 and controls all of the transfers of data from memory to processor and back. The purpose of this system is to utilize a multiprocessor to perform operations in a given algebraic expression in the least possible number of time units by performing certain of the operations in concurrent time periods.

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System Organization for Execution of Parallel Operations in Algebraic Statements

The system is a generalized machine organization for the execution of parallel operations in algebraic statements. There are included an indefinite number of processor s PROC 1... PROC N and a similar indefinite number of core memory units M1... MK as well as a Bus system tying these units to each other for data transfers. Program control is centralized in control unit 10 and controls all of the transfers of data from memory to processor and back. The purpose of this system is to utilize a multiprocessor to perform operations in a given algebraic expression in the least possible number of time units by performing certain of the operations in concurrent time periods.

To under stand this system operation. first take the following algebraic polynomial expression: a + bx + cx/2/ + dx/3/ + ex/4/

Performing the operations called for in the above expression would require fourteen separate calculations, if the expression were evaluated in the normal sequential manner. However, quite a large number of these expressions can be performed in parallel during relatively few time periods as shown in Table I. In this Table, each stage 1... 5 indicates those operations which can be performed in concurrent time periods, i. e., all of the operations within a given stage can be performed concurrently. It should be noted that a compiler or special purpose equipment would be necessary to provide the instruction list or compiled program illustrated in Table I.

Referring again to the machine organization for execution of the program as compiled in Table I, each processor is capable of fetching an instruction and two operands, decoding and executing the operation and returning the result to memory at a predetermined location. After such an operation, the processor becomes idle. When a processor completes an operation, it sends a complete signal to unit 10.

Unit 10 includes three counters X0, X1 and X2. Additionally, unit 10 has triggers for holding the completion reports from the various processors...