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Browse Prior Art Database

Flexible Storage Addressing

IP.com Disclosure Number: IPCOM000095693D
Original Publication Date: 1964-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Parsons, JF: AUTHOR

Abstract

As central processing units become faster and more complex, the number of required word storage positions becomes greater and greater since, due to low input-output speeds, more data and program words must be kept in storage. This situation is compounded when the processor is capable of multi-programming and program relocation functions which require more index registers and accumulator registers than are normally provided.

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Flexible Storage Addressing

As central processing units become faster and more complex, the number of required word storage positions becomes greater and greater since, due to low input-output speeds, more data and program words must be kept in storage. This situation is compounded when the processor is capable of multi- programming and program relocation functions which require more index registers and accumulator registers than are normally provided.

In the interests of economy and equipment utilization, however, instruction words must be limited to not more than the length of one or two data words. Such length is not enough to specify the addresses of the main storage address, the index register address and the accumulator address together with the operation code and other essential factors.

This arrangement uses much more addressable storage and many more index and accumulator registers than heretofore provided without the need for providing for corresponding addresses in the instruction word. Base Address Control Register 1 is supplied with connections to and from main storage and contains a portion of each of the addresses required in the current series of instruction words. Register 1 is loaded and unloaded by appropriate program instructions whenever there is a need in the current program for access to a different block of storage, index, or accumulator registers.

Instruction words are transferred from storage to the Instruction Register 2 under control of the usual program counter. The operation code part of the word is decoded in the Operation Decoder 3 to enab...