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Parity Checked Clock

IP.com Disclosure Number: IPCOM000095739D
Original Publication Date: 1964-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Brown, PJ: AUTHOR

Abstract

This circuit checks the operation of the Gray code counter described in IBM Technical Disclosure Bulletin, Vol. 5, No. 10, March 1963, Pages 52 and 53. In the Gray code counter, only one variable changes at a time. Therefore, a parity check of all the outputs of the counter and its drive yield a constant output. This is illustrated by the timing for the drive pulse input P and the output of the four stages A, B, C and D of the counter.

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Parity Checked Clock

This circuit checks the operation of the Gray code counter described in IBM Technical Disclosure Bulletin, Vol. 5, No. 10, March 1963, Pages 52 and 53. In the Gray code counter, only one variable changes at a time. Therefore, a parity check of all the outputs of the counter and its drive yield a constant output. This is illustrated by the timing for the drive pulse input P and the output of the four stages A, B, C and D of the counter.

The pulse input P and the outputs A, 13, C and D provide inputs to an even parity check circuit 1. This generates an output if there is a failure in any one of the inputs. The output of the parity check circuit feeds delay 2 which is inserted to filter transients that occur when the counter is stepped.

The length of delay is less than one-half the period of the pulses P. The output of the delay feeds one leg of And 3, the other leg of which is fed directly by the output of circuit 1. In the event any one of the inputs to circuit 1 fails, the parity is no longer even and an output occurs. Therefore, any single failure within the clock produces an error signal which has a minimum width of the drive pulse width minus the delay time of delay 2.

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