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Clock Pulse Checking circuit

IP.com Disclosure Number: IPCOM000095740D
Original Publication Date: 1964-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Bearnson, LW: AUTHOR [+2]

Abstract

This circuit checks two non-overlapping clock pulses for pulse dropout or pulse pickup errors. The waveforms A and B represent two stages of the clock. These two pulses are introduced on input lines 10 and 12 of And 14, the output of which drives Or 16. The two pulses are also directed to Or 18 which is connected to delay 20 having t units of time in length. The output 22 of Or 18 feeds And 24. The other leg of And 24 is energized by the output 26 of delay 20. The output of And 24 is inverted by inverter 28, the output of which drives another leg of Or 16.

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Clock Pulse Checking circuit

This circuit checks two non-overlapping clock pulses for pulse dropout or pulse pickup errors. The waveforms A and B represent two stages of the clock. These two pulses are introduced on input lines 10 and 12 of And 14, the output of which drives Or 16. The two pulses are also directed to Or 18 which is connected to delay 20 having t units of time in length. The output 22 of Or 18 feeds And 24. The other leg of And 24 is energized by the output 26 of delay
20. The output of And 24 is inverted by inverter 28, the output of which drives another leg of Or 16.

The timing drawing shows relative voltage potentials of the points A, B, C and D in the circuit. If there is no error, the pulses A and B never overlap. 1n that case, there is no output from And 14. The output of Or 18 is shown by curve C. This output is also delayed by t units of time as shown by curve B. The negative And function of curves C and D results in no output from And 24 and, hence, no output from inverter 28. If either pulses A or B overlap, an output occurs from And 14, thus giving an error indication on the output 30 of Or 16. If either or both of pulses A and B are missing, non-coincidence occurs at And 24, thus giving a negative output, which inverted, causes an output from Or 16 indicating error on line 30.

Examples of two different types of error conditions occurring on line B are shown by the timing. The first error condition shown is a partial dropout of the cloc...