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Subroutine Link

IP.com Disclosure Number: IPCOM000095743D
Original Publication Date: 1964-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Ottaway, GH: AUTHOR

Abstract

Choice of permanent addresses for micro-instructions, designated MI's, in control storage permits a single address value to identify the location of the MI used for subroutine entry setup and the location of the MI used for subroutine return through address modification techniques not involving incrementing.

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Subroutine Link

Choice of permanent addresses for micro-instructions, designated MI's, in control storage permits a single address value to identify the location of the MI used for subroutine entry setup and the location of the MI used for subroutine return through address modification techniques not involving incrementing.

Entry setup and return MI's for a subroutine are located at an address pair. The entry setup MI location address ends in 0. The return MI location address is identical except for ending in 1. Return from subroutine involves merely the forcing of a 1 in the low-order bit position. A designated invalid address identifies the last MI of a subroutine and initiates a simple operation to derive the address and force the low-order 1.

Nesting of subroutines within subroutines is controlled by a point field in which a number of locations in main memory is accessed in last-in-first-out fashion without the need for a decrementer. Subroutine Entry-Exit-Return.

A computer operating with a control storage unit ordinarily has a set of main instructions. Each controls major machine functions by ordering a series of MI's from control storage. Each MI provides a complete control over the gates of the computer during a single cycle and includes a low-order address field and two extra bits. One such extra bit is designated SR and is used to control subroutine entry setup by storing the return address. If, in the course of executing the sequence of MI's, the SR bit is 1, it forces an entry setup cycle. In the entry setup cycle, the point field and base address field of the current main instruction and the low-order address field of the current MI are stored in a designated main memory location. The next MI is then fetched according to the address specified by the base address and low-order address fields. The point field is set so that it points to the address in main storage, initially 000000, at which the return address is stored. Since each MI normally specifies the address of the next MI, the subroutine entry is performed as normal sequencing.

Return from the subroutine requires an identification of the final MI of the subroutine and a fetch of the return address stored in the main storage location specified by the point field. In control storage, the 111111 address is invalid. This all 1's address is assigned the return from subroutine meaning, and forces such return after its execution is completed. The content of the main storage location addressed by the value in the point field is fetched and replaces the current address value. The units position of the low-order address field is forced to the 1 value and the next MI fetched from this altered address.

The address specified in the MI containing the SR bit contains a low-order bit of value 0. The next control word to be executed is...