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A Counter Controlled Digital Averaging Buffer

IP.com Disclosure Number: IPCOM000095744D
Original Publication Date: 1964-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Dodd, PD: AUTHOR [+2]

Abstract

This is a buffer system for which either the input or the output is at a fixed rate, and the fixed rate is the average rate at the other terminal, i.e., a digital averaging buffer.

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A Counter Controlled Digital Averaging Buffer

This is a buffer system for which either the input or the output is at a fixed rate, and the fixed rate is the average rate at the other terminal, i.e., a digital averaging buffer.

In the figure, the source transmits the data Di, transfer pulse T(p) and reset pulse R(s). Clock generator 10 produces a four-phase clock. T1, T2 and T3 are the system synchronizing flip-flops. The buffer is register 12. The D counter 14 identifies the buffer position next to be filled. The B counter 16 coordinates readin with readout, the rate of which is constant. T3, in the reset state, inhibits T(p) from setting T2 during phases C(1), C(2) or C(3). This prevents simultaneously reading into and out of buffer 12. When T(p) arrives, data D(i) is held in storage until the next clock cycle; T3 is set by C4, permitting T(p) to indirectly set T2 and data D(i) to be read into buffer 12.

Buffer 12, as shown, assumes that, each time a T(p) occurs, two data bits are available and that the two data bits remain in storage outside the system for a duration of three bit periods and are shifted out under the control of counter 16.

The logic (all flip-flops are of the R-S type) is as follows: Synchronizing.
(1)t(1) = T(p)
(0)t(1) = R(s) + (B(1)'B(2))(Delayed)
(1)t(2) = T(p) T(3) + T(1) C(4)
(0)t(2) = R(s) + (B(1)'B(2))(Delayed)
(1)t(3) = C(4)
(0)t(3) = C(1)

B counter.
(1)b(1) = T(2) CB(1)'
(0)b(1) = R(s) + (B(1)'B(2))(Delayed) + T(2) C B(1)
(1)b(2) = B(...