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Instruction Unit

IP.com Disclosure Number: IPCOM000095761D
Original Publication Date: 1964-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Lindauer, SL: AUTHOR [+2]

Abstract

An instruction unit can operate at high speed, despite access time limitations of its buffer registers, by decoding in advance the class of the buffered instructions.

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Instruction Unit

An instruction unit can operate at high speed, despite access time limitations of its buffer registers, by decoding in advance the class of the buffered instructions.

In the instruction unit shown, instructions are derived from storage, four at a time. One instruction is performed immediately and the other three are stored temporarily in instruction buffer registers. These registers can be magnetic core registers which require a finite access time for readout to the instruction decoder.

This access time can be tolerated only if the decoder is sufficiently fast. To speed up the decoder, it is divided into two levels, a class level and a detail level. The class level takes its information from directly readable triggers; the detail level takes its information via the class level from the relatively slow access instruction buffer registers. The class information is available sufficiently early so that circuits can be set up to cut down propagation time through the decoder and other logic.

Storage unit 1 is accessed by instruction access unit 2 and provides, at one time, four instructions A, B, C, and D at storage data register 3. Instruction A is to be used immediately. Instructions B, C and D pass respectively to instruction buffer registers 4, 5 and 6 for later use. The instruction class bits of instructions A, B, C and D pass respectively to class decoders 7, 8, 9 and 10. Decoder 7 connects directly to the class level of the instruction decoder 11. Decoders 8, 9 and 10 connect respectively to class flag registers 12, 13 and 14.

In operation, the first instruction, Instruction A, passes through decoder 11, providing a class output and also providing an output to perform the function assigned to it. Flag registers 12, 13 and 14 continuously provide outputs indicative of the classes of their respective instructions to And's 15, 16 and 17, respectively. And's 15, 16 and 17 and buffer registers 4, 5 and 6 are scanned under control of scanning ring 18 to provide instructions in proper sequence from the instruction buffer registers. After the cycle in which Instr...