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Memory Accessing Technique

IP.com Disclosure Number: IPCOM000095810D
Original Publication Date: 1964-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Miller, RE: AUTHOR

Abstract

In the conventional operation of a destructive readout memory, such as a core memory, data is read out during the first half of a memory access cycle and then written back into the memory during the second half of the cycle. In this system, this process is modified to permit either the same or different information to be written into the memory during the second half of the memory cycle. In this manner, separate read and write operations that ordinarily require two memory access cycles can be performed in one cycle.

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Memory Accessing Technique

In the conventional operation of a destructive readout memory, such as a core memory, data is read out during the first half of a memory access cycle and then written back into the memory during the second half of the cycle. In this system, this process is modified to permit either the same or different information to be written into the memory during the second half of the memory cycle. In this manner, separate read and write operations that ordinarily require two memory access cycles can be performed in one cycle.

When the data that is stored in memory 1 at a location selected by addressing circuit 2 is to be replaced, the data is passed through gate 3 to read register 4 during the first half of the memory access cycle. The replacement data is supplied to the memory through gate 5 from write register 6 during the second half of the cycle.

For conventional memory accessing, during the first half of the cycle, the data from memory 1 is applied through gate 7 to the write register 6 in addition to being applied through gate 3 to read register 4. Thus, during the second half of the cycle, the same data is returned to the memory.

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