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Line Scanner Providing First In, First Out Service for Delayed Calls

IP.com Disclosure Number: IPCOM000095835D
Original Publication Date: 1964-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Abbott, GF: AUTHOR [+3]

Abstract

This is a line concentrator system which every call is served in the order in which it arrives in the system, irrespective of the length of time that it may wait for service. This is accomplished by storing the addresses in a recirculating memory as they occur, providing sufficient storage space for all addresses. A special marker indicates which is the first address stored. An address is taken from the specially marked position whenever a trunk becomes idle so that the first stored line can be connected to the first available trunk. The special marker is then moved to the next sequential address to cause that address to be served next.

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Line Scanner Providing First In, First Out Service for Delayed Calls

This is a line concentrator system which every call is served in the order in which it arrives in the system, irrespective of the length of time that it may wait for service. This is accomplished by storing the addresses in a recirculating memory as they occur, providing sufficient storage space for all addresses. A special marker indicates which is the first address stored. An address is taken from the specially marked position whenever a trunk becomes idle so that the first stored line can be connected to the first available trunk. The special marker is then moved to the next sequential address to cause that address to be served next.

Under normal operating conditions, a service request on any of fifty lines 1 sets a corresponding service request latch 2. Line scan drive 3 consists of a gated oscillator which drives binary counter 4. Counter 4 counts in modulo 50 and provides a fifty line output from scan decoder 5. When a coincidence of a latch 2 and the decoder 5 occurs, drive 3 is stopped by the inhibit line output of decoder 5. When drive 3 is stopped, the line address is in counter 4. Stopping drive 3 enables recirculating memory 10 to store the line address in the first empty time slot following a service marker under control of the address in logic 6. When the address has been stored, the latch 2 for that line is reset, causing drive 3 to be released.

Memory 10 can be an acoustical delay line, a magnetic storage device, or any other type of storage medium in which the cyclic operation consists of a shift cycle followed by an operational cycle.

During the shift cycle, information, i. e., address and markers, is shifted into and out of memory register 7 in normal shift register fashion. During the operational cycle the logic scans the contents of register 7 and takes action, i. e., store address or read out address, defined by address in logic 6 and address out logic 9.

In memory 10, each time slot is capable of storing one line address, six bits, and a coded marker, two bits. The marker is either a service or busy or idle or zero marker. There is only one service marker stored in memory which indicates the position of the next address to receive service. A busy marker is associated with any stored address, when the number of lines waiting to be served exceeds one. An idle marker indicates a time slot with no address in it. A zero marker is used to indicate an error.

When queueing an address, the memory circulates until the service marker is detected. Then the address is placed in the first zero address position following the service marker. This position is then tagged with a busy marker. Whenever the service marker is in register 7, if there is an idle trunk available, the line address associated with the service marker is transferred into line decoder 8 by a...