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Multiple Channel Correction of Burst Errors

IP.com Disclosure Number: IPCOM000095836D
Original Publication Date: 1964-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Wolff, CH: AUTHOR

Abstract

The error correction system is for use in writing and reading magnetic tape 9 having tracks 1... 16. Tracks 1... 8 record data bits B1... B8. Tracks 9... 16 record redundancy bits C1... C8. Thus, sixteen bits are recorded in parallel as a byte.

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Multiple Channel Correction of Burst Errors

The error correction system is for use in writing and reading magnetic tape 9 having tracks 1... 16. Tracks 1... 8 record data bits B1... B8. Tracks 9... 16 record redundancy bits C1... C8. Thus, sixteen bits are recorded in parallel as a byte.

Drawing 1 shows a circuit for generating redundancy bits C1... C8 from the data bits B1... B8 while recording tape. Each redundancy bit is generated by a Exclusive-Or (half adder) OE circuit that receives data bits spaced at least two tracks apart. The resulting redundancy bit is recorded on tape with a separation of at least two track widths from either of its data bits. In such case, up to three adjacent bits in a byte can be in error, and their correction can be obtained with this system.

Drawing 2 shows a system for correcting up to three adjacent bit errors in each byte read from tape. Data register 10 receives eight data bits B1... B8. Check register 11 receives eight redundancy bits C1... C8. Correction signal generator 12 locates erroneous bits in each received byte. Erroneous bits in the byte are corrected in correction circuit 13.

Drawing 3 shows a detailed portion of generator 12 having an array of Exclusive-Or groups 21a... and 22a... for summing each received redundancy bit with each data bit originally summed to provide the check bit. Redundancy bit C6 is summed with its data bits B1 and B4 in Exclusive-Or's 21a and 22a. Similarly, the redundancy bit C1 is summed wi...