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Fast Recovery Delay Circuit

IP.com Disclosure Number: IPCOM000095840D
Original Publication Date: 1964-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Curtis, JJ: AUTHOR [+2]

Abstract

This circuit has a pair of common emitter transistors T1 and T2. The collector of T1 is coupled to the base of T2 by way of capacitor 1 and a pair of diodes 2 and 3. Input signals are coupled to the base of T1 by way of resistor 4 and to junction 5 between capacitor 1 and diode 2 by way of diode 6. The collector of T1 is coupled to a positive potential by way of resistor 7. Capacitor 8 is connected between junction 5 and ground potential. Bias resistor 9 is connected between junction 5 and a positive supply potential. Resistor 10 is connected between the base of T2 and ground potential.

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Fast Recovery Delay Circuit

This circuit has a pair of common emitter transistors T1 and T2. The collector of T1 is coupled to the base of T2 by way of capacitor 1 and a pair of diodes 2 and 3. Input signals are coupled to the base of T1 by way of resistor 4 and to junction 5 between capacitor 1 and diode 2 by way of diode 6. The collector of T1 is coupled to a positive potential by way of resistor 7. Capacitor 8 is connected between junction 5 and ground potential. Bias resistor 9 is connected between junction 5 and a positive supply potential. Resistor 10 is connected between the base of T2 and ground potential.

The input signal is normally at ground potential. Such, forwardly biases diode 6 to maintain junction 5 at a potential which biases T2 at cut off. This input signal also maintains T1 cut off. When a positive going signal is applied to the input, T1 turns on to apply a negative signal to capacitors 1 and 8, establishing a negative potential at junction 5 which maintains T2 cut off. The value of the negative potential at junction 5 is determined by the relative values of capacitors 1 and 8, which values in this circuit are preferably equal.

Capacitors 1 and 8 now discharge through resistor 9. After a predetermined time delay, T2 turns on to produce a negative going pulse at its output terminal
11.

When the input signal returns to ground, diode 6 forwardly biases cutting T2 off. Capacitor 1 now charges through a circuit including diode 6 and resistor 7 whi...