Browse Prior Art Database

System of Half Duplex Operation of the Analog Derived Clock

IP.com Disclosure Number: IPCOM000095846D
Original Publication Date: 1964-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Anello, AJ: AUTHOR [+4]

Abstract

This system provides half-duplex serial data transmission between two synchronous transmitter-receiver (STR) stations. The circuit maintains the receive clock synchronized during transmission of signals in the absence of data on the receive data input. A local STR station is shown in detail. The remote STR 2 is identical to the local station.

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System of Half Duplex Operation of the Analog Derived Clock

This system provides half-duplex serial data transmission between two synchronous transmitter-receiver (STR) stations. The circuit maintains the receive clock synchronized during transmission of signals in the absence of data on the receive data input. A local STR station is shown in detail. The remote STR 2 is identical to the local station.

Initial synchronization is accomplished by throwing switch SW1 to send position S, switch SW2 to receive position R and SW3 to receive position R. STR 2 transmits idle signals to the local STR to achieve synchronization. The mark-space condition of the serially received signal elements on line 10 is applied to And's 11 and 12. Here the condition of the signal element is sampled by a sample pulse generated from a reference signal source produced from multivibrator 14. The signal elements received on line 10 are subject to distortion. However, the pulse output from inverter 17 samples these signals at their midpoint to produce a reconstruction of the received signal which is accurately timed and free of distortion. This is accomplished by applying the signal on line 10 to And 11 and inverter 13. The output of inverter 13 is applied to And 12. The output of inverter 17 then sets the condition of line 10 into line trigger 18 by energizing And's 11 and 12.

The mark and space condition of the received signal element on lines 10 and 24, the reference mark and space 16 from multivibrator 14, the distortion free reconstructed data output signal 20 from line trigger 18 and its inversion 22 from inverter 23 are combined in binary logic 25 to produce an indication of the relationship between the signals. This is described in more detail in the IBM Journal of Research and Development, July 1964, by the paper on pages 318 - 328 by Anello, Ruocchio, and Van Gieson, Jr.

Binary logic 25 produces as an output either a voltage +V, -V or no output. The output of binary logic 25 is applied to mixer 28 via lines 26 and 27. The output of mixer 28 is a reference potential, either +V or -V, representing the relationship between the mark-space condition of the signals applied to binary logic 25. The output 29 of mixer 28 is applied to filter 30 which develops a varying output signal 31 that is the average value of the three-level signal applied at its input. Output 31 of filter 30 represents the relationship between the sample pulse produced by inverter 17 and the center of the received signal elements on line 10. Output 31...