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Error Free Operation With Imperfect Memory Arrays

IP.com Disclosure Number: IPCOM000095895D
Original Publication Date: 1964-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Chien, RT: AUTHOR

Abstract

Circuit 8 obtains error-free operation of a batch-fabricated memory system with imperfect arrays. Generally, the imperfect locations occur in bursts. The information stored at any location tends to be either a 1 or a 0 permanently.

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Error Free Operation With Imperfect Memory Arrays

Circuit 8 obtains error-free operation of a batch-fabricated memory system with imperfect arrays. Generally, the imperfect locations occur in bursts. The information stored at any location tends to be either a 1 or a 0 permanently.

If the maximum number of erroneous bits in an addressable array of n-bits is b, the memory is organized with b adjacent bits at the end of the array reserved as interlaced parity bits. Each parity bit checks every b-th bit counting from itself. The first bit is a parity check on the bits n, n-b, n-2b... In the read operation, the information is transferred from memory 10 to register 12. It is also transferred from memory 10 to register 14 after an attempt to complement the information is made. The contents R1 and R2 of registers 12 and 14 are compared by comparison unit 16. The contents of register 12 are error-free if they are the complement of the contents of register 14 and they are read out via Exclusive Or
20.

If the contents R1 and R2 of registers 10 and 12 are not complementary, an error has been detected by circuit 8. As each parity check made by parity check unit 24 covers every b-th bit, there is no more than one erroneous bit in each parity equation. The locations of the erroneous bits are determined by unit 16. The parity checks from unit 24 are used to correct the erroneous positions by controlling gate 18. This provides the correct bit to Exclusive Or 20.

In an alternative...