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Browse Prior Art Database

Multiplier

IP.com Disclosure Number: IPCOM000095898D
Original Publication Date: 1964-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Fleisher, H: AUTHOR [+2]

Abstract

This multiplier consists of the following four main sections. In the first, memory 200 has registers 201...205 for storing all of the possible partial products of the multiplicand. Registers 206 and 207 are for storing first and second order carries. Register 208 is for storing the product. The various possible partial products in a binary system are generated by shifting the multiplicand. The content of any column of memory 200 is read out on lines 281...287 by activating one of lines 221...230.

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Multiplier

This multiplier consists of the following four main sections. In the first, memory 200 has registers 201...205 for storing all of the possible partial products of the multiplicand. Registers 206 and 207 are for storing first and second order carries. Register 208 is for storing the product. The various possible partial products in a binary system are generated by shifting the multiplicand. The content of any column of memory 200 is read out on lines 281...287 by activating one of lines 221...230.

In the second section, masking register 300 is for storing the multiplier. Any digit of the multiplier which is zero disables, i.e., masks, the associated memory output line 281. . . 285. In section three, logical adder 400, e.g., an adding matrix, sums the signals on lines 381...387 and produces the sum in a 1 out of N code on lines 401.. .406. In section four, decoding matrix 500 takes the sum expressed in a 1 out of N code on lines 401...406 and decoding matrix 501 stores multiplicand, sum and carry digits in the appropriate orders of the registers 206, 207 and 208.

A multiplication is performed by sequentially reading out the columns of memory 200, starting with the lowest order column. The signals on lines 381...387 from the various rows of memory 200, as masked by register 300, are summed by adder 400. The resulting carries, after being decoded by circuits 500 and 501, are stored in the appropriate digital positions of registers 206 and 207. The sum digi...