Browse Prior Art Database

Fabrication of a Gated Field Effect Solid State Device

IP.com Disclosure Number: IPCOM000095922D
Original Publication Date: 1964-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Maissel, LI: AUTHOR [+2]

Abstract

The method produces gated field effect solid state devices, which method minimizes the presence of stress points within the device and reduces the opportunities for electrical breakdown.

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Fabrication of a Gated Field Effect Solid State Device

The method produces gated field effect solid state devices, which method minimizes the presence of stress points within the device and reduces the opportunities for electrical breakdown.

The method entails depositing a gate metal 2, such as tantalum niobium, aluminum onto a support 4 by one of the conventional techniques, such as vacuum evaporation, cathode sputtering, or electrodeposition. Surface 6 of gate metal 2 is covered with photoresist 8 or other masking material such as in A and is etched to the desired pattern. Assembly A comprising gate metal 2 and superimposed photoresist 8 is then immersed as an electrode in an anodization electrolysis cell.

A positive bias is applied to metal 2 with respect to a second electrode immersed in the cell. The bias is maintained until a desired thickness of oxide 10 grows about the sides 12 of metal 2 and beneath the periphery 14 of masking layer 8 as in 13. That oxide 11 which creeps under masking layer 8 serves to decrease the sharpness of the edge contours 3 and, in turn, lessen the regions of high stress about gate metal 2. Masking layer 8 is then removed, and, the anodization process repeated at lower voltage to complete the growth of the oxide about the surface 16 of metal 2 as in C.

A semiconductor layer 18 such as CdS, CdTe, Se is superimposed about oxide layer 10, see D. The fabrication of the device is then completed with the evaporation of a metal 20 such a...