Browse Prior Art Database

Frequency Doubler

IP.com Disclosure Number: IPCOM000095924D
Original Publication Date: 1964-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Pennebaker, WB: AUTHOR

Abstract

A frequency doubler circuit arrangement is illustrated in A which comprises thin film transistor 1 having an active layer 3 of semiconductor material. Active layer 3 exhibits a conductivity 0 which varies as a function of gate-bias voltage V as illustrated in B. When gate-bias voltage V(g) is positive with respect to that gate-bias voltage corresponding to minimum conductivity, transistor 1 exhibits N-type operation. When gate-bias voltage V(g) is negative with respect to that gate-bias voltage corresponding to minimum conductivity, transistor 1 exhibits P-type operation.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Frequency Doubler

A frequency doubler circuit arrangement is illustrated in A which comprises thin film transistor 1 having an active layer 3 of semiconductor material. Active layer 3 exhibits a conductivity 0 which varies as a function of gate-bias voltage V as illustrated in B. When gate-bias voltage V(g) is positive with respect to that gate-bias voltage corresponding to minimum conductivity, transistor 1 exhibits N- type operation. When gate-bias voltage V(g) is negative with respect to that gate-bias voltage corresponding to minimum conductivity, transistor 1 exhibits P- type operation.

Depending upon the magnitude of AC signal applied to gate electrode 5 by source 7, the circuit arrangement is operative either as (1) a a linear amplifier, (2) a half-wave rectifier or (3) a full-wave rectifier. Referring to 13, transistor 1 operates as a linear amplifier when the applied gate-bias voltage V(g) is between a and a'.

When the applied gate-bias voltage V(g) is between points b and b', transistor 1 amplifies only positive excursions of the AC signal to effect half-wave rectification.

When applied gate-bias voltage V(g) is in excess of region bb', e.g., region cc', transistor 1 amplifies both positive and negative excursions thereof. The amplified negative excursion is out of phase with respect to the amplified positive excursions so that full-wave rectification, i.e., frequency doubling, is achieved.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-tex...