Browse Prior Art Database

Method of Matching the Gate to the Source Drain Ga in a Tft

IP.com Disclosure Number: IPCOM000095925D
Original Publication Date: 1964-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Seki, H: AUTHOR

Abstract

This photolytic method is for matching the effective gate area with the source-drain gap of a thin film transistor so as to minimize input gate capacitance.

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Method of Matching the Gate to the Source Drain Ga in a Tft

This photolytic method is for matching the effective gate area with the source-drain gap of a thin film transistor so as to minimize input gate capacitance.

A first technique is illustrated in A in which the thin film transistor is formed having an overlapping gate electrode 1. Layer 3 of positive photoresist material and opaque metallic layer 5 are deposited over gate electrode 1, layer 5 being deposited through the source-drain mask. Layer 3 of photoresist material is then exposed to sensitizing light and developed. Unsensitized portions of it, along with metallic layer 5 and overlapping portions of gate electrode 1, are chemically etched so that the effective gate area is matched with source-drain gap 7.

A second technique is illustrated in B in which source and drain electrodes 9 and 11 are deposited to be opaque. Layer 13 of negative photoresist material is deposited over thin insulating layer 15 and active layer 17, both being transparent to sensitizing light.

Layer 13 of photoresist material is exposed to sensitizing light, as shown, through the source-drain pattern which serves as an optical mask. Sensitized portions of layer 13 of photoresist material are removed by development. Subsequently, gate electrode 19 is deposited to overlap portions of layer 13 of photoresist material so that portions of it, contiguous with thin insulating layer 17, are matched with source-drain gap 21.

A third techniq...