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Program Instruction Time Down Device

IP.com Disclosure Number: IPCOM000095932D
Original Publication Date: 1964-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Pung, BD: AUTHOR [+2]

Abstract

In computer systems which have remote communication equipment, message processing operations are sometimes required to be completed within a predetermined length of time. In some cases, a multiple-computer configuration is involved. A circuit for determining whether either or both computers of a communication data processing system are operating within proper time periods is shown. CPU 1 will send a program timing pulse over line 10 to And 12. This is responsive, when latch 14 is turned off, to generate a signal for setting latch 14. This then identifies and registers the first program timing pulse sent from CPU 1. The output of And 12 also starts a time out circuit 16. This generates a first timing signal T1 on line 18 after a first predetermined time interval.

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Program Instruction Time Down Device

In computer systems which have remote communication equipment, message processing operations are sometimes required to be completed within a predetermined length of time. In some cases, a multiple-computer configuration is involved. A circuit for determining whether either or both computers of a communication data processing system are operating within proper time periods is shown. CPU 1 will send a program timing pulse over line 10 to And 12. This is responsive, when latch 14 is turned off, to generate a signal for setting latch 14. This then identifies and registers the first program timing pulse sent from CPU 1. The output of And 12 also starts a time out circuit 16. This generates a first timing signal T1 on line 18 after a first predetermined time interval. It also generates a signal T2 on line 20 after a second predetermined interval. These timing relationships are shown in the lower drawing.

The circuit interrupts CPU 1 and CPU 2 whenever a second CPU program timing pulse appears on line 10. This occurs at any time other than the period P between the T1 and T2 signals as shown. Signal T1 on line 18 sets latch 22 which, together with a reset condition of latch 24 causes And 26 to be responsive to the second program timing pulse 10 as it passes through And 28. Thus, And 28 recognizes the second program timing pulse. If this appears after T1 is turned on and before T2 is turned on, then And 26 generates a signal which indi...