Browse Prior Art Database

Counter

IP.com Disclosure Number: IPCOM000095939D
Original Publication Date: 1964-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Owen, CE: AUTHOR

Abstract

The counter has a number of And's 2 connected to latches 3. Each latch is set to provide a 1 output signal A, B, C, and D upon receipt of an input signal at its set input or a 0 output signal A, B, C, and D upon receipt of an input signal at its reset input. The outputs from the latches are applied back to the And inputs as shown.

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Counter

The counter has a number of And's 2 connected to latches 3. Each latch is set to provide a 1 output signal A, B, C, and D upon receipt of an input signal at its set input or a 0 output signal A, B, C, and D upon receipt of an input signal at its reset input. The outputs from the latches are applied back to the And inputs as shown.

To increment the counter, pulses P(0) and P(1) are applied alternately. Thus, in response to these pulses the counter counts in a modified reflected binary code as shown in the following table: DRNE PULSE LATCH OUTPUTS A B C D P(0) 0 0 0 0 P(1) 0 0 0 1 P(0) 0 0 1 1 P(1) 0 0 1 0 P(0) 0 1 1 0 P(1) 1 1 1 0 P(0) 1 0 1 0 P(1) 1 0 1 1 P(0) 1 0 0 1

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