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Browse Prior Art Database

Parametron Circuits

IP.com Disclosure Number: IPCOM000095952D
Original Publication Date: 1964-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Horgan, TB: AUTHOR

Abstract

In counters, it is often desirable to have the outputs available at the same time. Since the Phase Locked Oscillators (P/LO's) of a multistage P/LO counter are respectively pumped on different subcycles, the outputs are likely to occur at different subcycles of the usual three-subcycle clock system. The sub-cycles occur only one at a time with a definite overlap between them.

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Parametron Circuits

In counters, it is often desirable to have the outputs available at the same time. Since the Phase Locked Oscillators (P/LO's) of a multistage P/LO counter are respectively pumped on different subcycles, the outputs are likely to occur at different subcycles of the usual three-subcycle clock system. The sub-cycles occur only one at a time with a definite overlap between them.

A parallel arrangement of P/LO counter stages 1, 2, 4 and 8 for the 1, 2, 4 and 8 bits is shown in A. Delay between stages is minimized. The basic circuit for this parallel counter is represented, e. g., by stage 4 which comprises five P/LO's with P/LO's 4a... 4d forming a flip-flop. This advances whenever an advance signal Adv coincides with a carry input. Such is produced by 4e which is conditioned when the preceding stages are full. This P/LO for the general case must And N-1 inputs, which for the third stage results in two inputs. This simplifies to the four P/LO arrangement of stage 1 and 2, as N-1 equals 0 and 1, respectively, neither of which requires the fifth carry P/LO.

The first Adv pulse is applied to all four stages. At subcycle 1, 1a turns on followed by 1b and 1c on successive subcycles to raise the 1 output. If no further Adv pulses occur, 1d is turned on at the next occurrence of subcycle 1, followed by 1b and 1c on successive subcycles turns on followed by 1b and 1c on successive subcycles to raise the 1 output. If no further Adv pulses occur, 1d is turned on at the next occurrence of subcycle 1, followed by 1b and 1c on successive subcycles in a closed ring to maintain the 1 output. Upon occurrence of the next Adv pulse, 1a is turned off as is 1d in subcycle 1. This turns off 1b and 1c on successive subcycles. At the same time the second Adv pulse is applied to 2a during subcycle 1 and turns 2a on as 2c is off and 1c is on. This causes 2b and 2c to be turned on during successive subcycles to raise the 2 output. The several stages are turned on and off alternatively, 4e and 8e serving to indicate to their respective stages that all preceding stages are on.

A s...