Browse Prior Art Database

Correction of Memories with Defective Bits

IP.com Disclosure Number: IPCOM000095990D
Original Publication Date: 1964-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Evans, J: AUTHOR [+3]

Abstract

The circuit obtains a correct readout from a word position in main memory 10 having one or more defective bit positions. Each word having a defective position in memory 10 is stored in adjunct memory 12. The address of the word in memory 10 having the defective bit is stored with the corresponding word in memory 12. Address transform circuit 14 is of a type which converts the input address applied to it into a unique address in memory 12. If the input address applied to MAR is one which is contained in memory 12, transform circuit 14 causes this entry in memory 12 to be read out into register 16.

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Correction of Memories with Defective Bits

The circuit obtains a correct readout from a word position in main memory 10 having one or more defective bit positions. Each word having a defective position in memory 10 is stored in adjunct memory 12. The address of the word in memory 10 having the defective bit is stored with the corresponding word in memory 12. Address transform circuit 14 is of a type which converts the input address applied to it into a unique address in memory 12. If the input address applied to MAR is one which is contained in memory 12, transform circuit 14 causes this entry in memory 12 to be read out into register 16.

In operation, the input address applied to MAR causes the word at that address in memory 10 to be read out into data register 18 and also causes transform circuit 14 to generate an address, causing a readout from memory 12. A comparison is then performed in compare circuit 20 between the address in MAR and the address read out from memory 12 into register 16.

If these two addresses are the same, then the word in memory 10 has a defective bit position. Gate 22 is conditioned to pass the data from memory 12 contained in register 16 to output buffer 24. If the addresses applied to compare circuit 20 are not the same, then there are no defective bits in the accessed position in memory 10. Gate 26 is conditioned to pass the word from memory 10 contained in register 18 to buffer 24.

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