Browse Prior Art Database

Memory Strobe Control

IP.com Disclosure Number: IPCOM000095998D
Original Publication Date: 1964-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Sakalay, FE: AUTHOR

Abstract

Connecting an open-ended delay line in parallel with the strobed output of a memory sense amplifier permits a choice of two memory output timings.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Memory Strobe Control

Connecting an open-ended delay line in parallel with the strobed output of a memory sense amplifier permits a choice of two memory output timings.

The output of sense amplifier 1 connects to And 2 in standard fashion. A normal strobe pulse at sense amplifier output time gates the sense amplifier output toward the memory register. Open-ended delay line 3 is also connected to the output of amplifier 1. The output of amplifier 1 passes through line 3 to the open end, is reflected back, and provides the sense amplifier output, delayed two delay periods, again to And 2. A delayed strobe pulse at this time gates the reflected delayed sense amplifier pulse on toward the memory register. The memory output thus is available at two distinct times.

Taking memory outputs at different times provides opportunity for making a logical decision based upon a small number of bits prior to the entry of the entire memory word into the memory register. This is useful in implementing memory protection techniques, particularly those aimed at protecting stored information from destruction because of a machine error in addressing.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]