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Threshold Carry Look Ahead for Parallel Binary Adder

IP.com Disclosure Number: IPCOM000096000D
Original Publication Date: 1964-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Schmookler, M: AUTHOR

Abstract

This is a threshold carry look-ahead circuit which generates a carry output from a parallel binary adder in one level of logic delay.

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Threshold Carry Look Ahead for Parallel Binary Adder

This is a threshold carry look-ahead circuit which generates a carry output from a parallel binary adder in one level of logic delay.

At A, the simultaneous parallel adder is divided into three groups having four operand inputs each, e. g., X1...X4 and Y1... Y4 in group GR1. Each adder group generates the sum for the respective operand inputs and also two special carry look-ahead functions. The carry propagate function Cp indicates that a carry inserted to the low-order position of an adder group propagates down the entire length of the group and exits from the high-order end. The carry generate function CG indicates that a carry is generated within the group and passed to the next succeeding group. By utilizing these functions, the end carry Co of the entire adder can be simultaneously generated with the generation of the discrete sums. This is accomplished by utilizing the Boolean function, shown at B, which expresses the end carry in terms of the carry generate and carry propagate functions.

To implement this Boolean function, threshold circuit T is used in combination with inputs which are weighted in accordance with the carry propagate and generate functions as they are derived from groups GR1... GR3 of the parallel adder. An optimum assignment of input weights to circuit T is made as follows. The carry in C(i) and the carry propagate function C(G1) derived from GR1 are each assigned the value of 1. Each s...