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Browse Prior Art Database

Memory Block Interchange and Interlace

IP.com Disclosure Number: IPCOM000096003D
Original Publication Date: 1964-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Johnson, HG: AUTHOR

Abstract

This memory addressing apparatus interchanges and interlaces blocks of core storage in various combinations under program control. lt further permits the discontinuance of interlace in the event of failure of one block of storage.

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Memory Block Interchange and Interlace

This memory addressing apparatus interchanges and interlaces blocks of core storage in various combinations under program control. lt further permits the discontinuance of interlace in the event of failure of one block of storage.

Memory address register 10 temporarily stores a memory address which specifies a certain memory block and the position within that block which holds the desired information. Four memory blocks 15... 18 are shown. Any one of these can be designated by the two low-order bits of the memory address, e. g., memory block 16 is designated by the low-order bits 01. An And matrix is contained within the address interlacing circuits 20 and provides the function of directing sequential addresses to sequential memory blocks. Memory interlace requires that successive addresses be placed in successive memory blocks so that the cycle time of any one memory block is not a limiting factor in the overall memory cycle time. Thus, the address interlacing circuits 20 examine the two low-order bits of register 10 and direct the address sequentially to the numbered memory blocks.

It is sometimes desired to interlace blocks by pairs, to have no interlacing, or to interlace discrete ones of the blocks. This function is provided by either program control or manual control of the energization of one of function control lines 22. Thus, by energizing the First Two line, only memory blocks 15 and 16 are interlaced. That is, add...