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Browse Prior Art Database

Simultaneous Address Relocation and Correction

IP.com Disclosure Number: IPCOM000096014D
Original Publication Date: 1964-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Boland, LJ: AUTHOR [+2]

Abstract

This address arithmetic arrangement permits a two-input adder to effect a single cycle address correction requiring a consideration of three factors.

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Simultaneous Address Relocation and Correction

This address arithmetic arrangement permits a two-input adder to effect a single cycle address correction requiring a consideration of three factors.

To adapt a single program processing computer to multiprogramming applications, it is desirable to provide a relocate feature for the machine. This feature allows the supervisory program to alter the assigned addresses of the instructions to suit the available memory locations as various programs are completed while others are still in process. Two separate arithmetic operations must be performed to accomplish this function.

The first is an addition in which a relocate increment is added to the high- order bits of the address. For instance, as shown at A, the address is fifteen bits long and a relocate increment is added to the high-order seven bits B1. It also quite often occurs that the low-order bits of the address 1...8 are incorrect due to certain machine functions and must be corrected. For instance, if on the prior program step two words were simultaneously accessed, the program counter incremented by a factor of two, and only the first word of the two withdrawn from the memory used, then the program counter indication is one too high. This counter must be decremented by a factor of one. It can also occur that the program counter indication is too small and must be incremented. In either case, the address correction is added to the low-order eight bits of the address B2.

As shown at C, the above defined arithmetic operations are accomplished in a two-input adder. The address is applied to one input and the relocate increment and correction factors are applied to the other input. So long as the address correction requires only a simple...