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A Transistor Tunnel Diode Cell for Associative Memories and Multiple Word Access Memories

IP.com Disclosure Number: IPCOM000096069D
Original Publication Date: 1964-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Wang, CP: AUTHOR [+2]

Abstract

The high-speed nondestructive memory cell of A comprises a tunnel diode 1, operable in a bistable mode, and driving transistors Tx and Ty. The anode of diode 1 is connected to bias source Vb along resistor Rb and, also, to the emitters of Tx and Ty along resistors R1 and R2, respectively. The collector of Tx is connected along sense line S and resistor R3 to voltage source Vx. The collector of Ty is connected along resistor Ry to voltage source Vy. Drive lines X and Y are connected to the base electrodes of Tx and Ty, respectively, and are normally biased to maintain the transistors cut off regardless of the operating state of diode 1.

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A Transistor Tunnel Diode Cell for Associative Memories and Multiple Word Access Memories

The high-speed nondestructive memory cell of A comprises a tunnel diode 1, operable in a bistable mode, and driving transistors Tx and Ty. The anode of diode 1 is connected to bias source Vb along resistor Rb and, also, to the emitters of Tx and Ty along resistors R1 and R2, respectively. The collector of Tx is connected along sense line S and resistor R3 to voltage source Vx. The collector of Ty is connected along resistor Ry to voltage source Vy. Drive lines X and Y are connected to the base electrodes of Tx and Ty, respectively, and are normally biased to maintain the transistors cut off regardless of the operating state of diode 1.

The operation of the memory cell is illustrated in B. To effect a read operation, a positive interrogation pulse is applied along line X. This pulse drives Tx into conduction only when diode 1 is operating in the low voltage 0 state so that a negative information pulse is directed along line S.

To effect a write operation, a negative clear pulse is initially applied at terminal R to reset diode 1 to the low voltage 0 state. To write 1, positive pulses applied coincidently along lines X and Y drive Tx and Ty, respectively, into conduction and cause diode 1 to switch to the high voltage state. To write 0, line X is singularly energized and the resulting conduction of Tx is ineffective to switch diode 1 to the high voltage 1 state.

The memory cell of A can be modified as in C to provide a special function capable of simultaneous access to two word addresses in a memory. A pair of driving transistors Tx1 and Tx2 are substituted for...