Browse Prior Art Database

Digital Deflection System

IP.com Disclosure Number: IPCOM000096075D
Original Publication Date: 1964-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Westbrook, RO: AUTHOR

Abstract

The circuit is for use with a cathode ray tube, in which digital deflection is provided by current outputs from a binary counter via weighted current decoders. In systems of this type, the ripple time involved in setting the last few counter stages is long enough that deflection current, produced by the lower order stages being reset, starts to decay before it is replaced by the higher order stage being set. This results in undesirable bar-like patterns on the CRT raster. This circuit shortens the ripple time to selected higher order stages of the counter through auxiliary logical connective devices.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 64% of the total text.

Page 1 of 2

Digital Deflection System

The circuit is for use with a cathode ray tube, in which digital deflection is provided by current outputs from a binary counter via weighted current decoders. In systems of this type, the ripple time involved in setting the last few counter stages is long enough that deflection current, produced by the lower order stages being reset, starts to decay before it is replaced by the higher order stage being set. This results in undesirable bar-like patterns on the CRT raster. This circuit shortens the ripple time to selected higher order stages of the counter through auxiliary logical connective devices.

The deflection system includes a binary counter made up of ten cascaded triggers, each of which is operated by a positive level change at the input. Repeated pulsing of the input of the first trigger produces a binary progression of signals from the true outputs of the triggers. These outputs are fed via correspondingly weighted decoders, D1..D10, to the Summing Circuit. The summed currents are fed into the horizontal CRT deflection coils for providing the required digital scan.

Stages 1...7 of the counter are binary-connected and operated in the conventional manner. The last three triggers are not binary-connected, but have separate set and reset input lines. Early operation of T8, T9 and T10 is achieved by circuits which determine that all lower order triggers have been set and are being reset. The precise setting time is controlled by the...